* Finite State Machines - Meely/Moore
* Synchrnous vs Asyncrnous Communications
* Sequence Detection
* Adder/ Subtractors to ALU's
* Digital/FPGA Memory
* Timing & Resets
* System Verilog HDL syntax and structure
* Testbenchs
* Quartus Prime Software
* ModelSim and Do files
* Altera FPGA Boards
* FPGA Engineers Puzzle Box | Paper | Presentation Slides |